1. Field of the Invention
The present invention relates to a solid state image sensing device capable of producing a high quality picture, and more particularly to an image sensor associated with the CMOS technology and an equivalent potential diode.
2. Description of the Related Art
With the development of telecommunication and computer systems, CMOS image sensors can be utilized in electronic imaging systems. The demand for CMOS image sensors will increase in proportion to the rate of development of digital still cameras, PC cameras, digital camcoders and PCS (personal Communication Systems), as well as standard analog and advanced digital TV and video systems. Further, the CMOS image sensor can be used in video game machines, security cameras and micro cameras for medical treatment.
FIG. 1 is a block diagram illustrating a conventional CCD (Charge Coupled Device) image sensor. As shown in FIG. 1, the CCD image sensor 100 includes a photoelectric conversion and charge accumulator 10 for absorbing light from an object and collecting the photogenerated charges into signal charge packets. Also, the CCD image sensor 100 includes a charge transfer region 20 to convey charge packets from the photoelectric conversion and charge accumulator 10 and a charge-to-voltage signal converter 30 to generate a voltage output of the signal charge packets as transferred through the charge transfer region 20.
A photodiode is widely used as a photoelectric conversion and charge accumulator. The photodiode having a PN junction forms a potential well to accumulate the charges generated by light from the object. The charges generated in the photoelectric conversion and charge accumulator 10 are trapped in the potential well of the photodiode and the trapped charges are transferred to a desired position according to the movement of the potential well. Such a charge movement is controlled by the charge transfer region 20.
The charge-to-voltage signal converter 30 generates a voltage that is related to the transferred signal charge packets. Since electric charges generate an electric field which corresponds to an electrostatic potential, the change in electric charge concentration as a result of introducing a signal charge packet can be measured by the change in the electrostatic potential (i.e. the depth of the potential well). This potential well depth variation contributes to voltage detection in the CCD image sensor.
After detecting the signal, the charges in the current potential well must be removed for subsequent signal detections. This removal of the charges is achieved by flushing the signal charge packet into a drain. By lowering the potential barrier between the potential well and the drain, the potential well can be "reset".
As stated above, the conventional CCD image sensor detects the image signals through the charge coupling. The photodiode, which acts as a photosensitive plate corresponding to an image pixel, does not immediately extract photoelectric current, but extracts it after the charges are accumulated for a predetermined time into a signal packet. Accordingly, the CCD image sensor has a good sensitivity with low noise. However, since the CCD image sensor must continuously transfer photoelectric charge packets, the required driving signals are very complicated, require large voltage swings of approximately 8V to 10V, have high power consumption, and require both positive and negative power supply. Compared with submicron CMOS technology which needs about 20 photomasks, CCD technology is more complicated and also more expensive due to additional photomask processes (about 30 to 40 photomasks). In addition, since the CCD image sensor chip can not be integrated with signal processing circuitry which is typically implemented by CMOS circuitry, it is very difficult to miniaturize the size of the image sensor and implement in a wider variety of applications.
Accordingly, a wider and deeper study of the APS (active pixel sensor), which is controlled by the switching operation of a transistor, has been made with the combination of the CMOS and CCD technologies.
FIG. 2 is a circuit diagram illustrating a unit pixel of the conventional APS proposed by U.S. Pat. No. 5,471,515 of Fossum, et al. The APS uses a photogate 21 of the MOS capacitor structure to collect photoelectric charges. In order to transfer the charges generated under the photogate 21 to a floating diffusion region 22, the APS includes a transfer transistor 23. Also, the APS includes a reset transistor 24, a drain diffusion region 25, a drive transistor 26 acting as a source follower, a select transistor 27 to select a pixel array row, and a load transistor 28.
However, in the APS as shown in FIG. 2, the MOS capacitor, which acts as a photosensitive plate, is made of a thick polysilicon layer so that a large fraction of blue light (with a shorter wavelength than red light) is preferentially absorbed by the polysilicon. As a result, it is difficult to obtain high quality color images at low illumination.
FIG. 3 is a cross-sectional view of the APS proposed by U.S. Pat. No. 5,625,210 of Lee, et al. U.S. Pat. No. 5,625,210 disclosed the APS with a well-known pinned photodiode. The APS in FIG. 3 includes a pinned photodiode (PPD) to collect the photoelectric charges and a transfer transistor T.sub.x having an N.sup.- region 36 for transferring the photoelectric charges from the PPD to a floating N.sup.+ region 37 of an output node. There is provided a reset transistor having the N.sup.+ region 37 for one active region and also having an N.sup.+ region 38 for another active region coupled to a power supply VDD. The impurities are introduced into a lightly doped P-epi (epitaxial) layer 32 which is grown on a more heavily doped P-type substrate 31. The PPD is formed by a buried N.sup.+ region 33 and a P.sup.+ pinning region 34. Additionally, in FIG. 3, each of the reference numerals 35a, 35b and 35c denote a transistor gate.
Specifically, as shown in FIG. 4 and in U.S. Pat. No. 5,625,210 of Lee, et al, the PPD is formed by sequential ion implantation of N.sup.+ and P.sup.+ impurities, using a single mask layer 41 (e.g., photoresist pattern). In particular, the PPD is formed by only one mask for both N.sup.+ and P.sup.+ ion implantation processes.
However, if the N.sup.+ and P.sup.+ ion implantation are sequentially performed using only one mask, the P.sup.+ pinning region 34 formed above the N.sup.+ region 33 will not be reliably electrically connected to the P-epi layer 32. Especially, since a higher energy is used to implant the N.sup.+ region 33 compared with the P.sup.+ pinning region 34, such ion implantation processes will result in the P.sup.+ pinning region 34 being electrically isolated from the P-epi 32. As a result, the P.sup.+ pinning region 34 and the P-epi layer 32 will be at different potentials especially when using a low power supply of 3.3V. This difference in potential prevents the full depletion of the N.sup.+ region 33 and, therefore, a stable pinning voltage can not be obtained. Furthermore, dopant segregation of boron atoms into the field oxide layer 39 may also contribute toward isolating the P.sup.+ pinning region 34 from the P-epi layer 32.
Another U.S. Pat. No. 5,567,632 of Nakashiba and Uchiya disclosed the buried (or pinned) photodiode fabricating method, which employs inclined ion implantation and a single mask layer. In this case, it is difficult to control and monitor the ion implantation angle in a mass production environment. That is, it is very difficult to measure the precise alignment of the N.sup.+ pinning region 34 and the P.sup.+ region 33 and to make the buried photodiodes uniform and reliable. In addition, the use of an angled ion implantation of either N.sup.+ or P.sup.+ limits the placement of the transfer gate to a specific orientation relative to the chip and wafer due to the angled ion implantation.